Re: [f-cpu] Status quo

[Nicolas Boulay <nicolas@xxxxxxxxxxx>]

GPUÂ use a specific memory layout "in Z" to favor locality access and caching. This is simple "tiling". When you copy this kind of image between cpu and gpu memory, the pixel must be moved to the right place. And it's slow.

Tiling is a good also for cpu code on image. Using tiling "by hand" in cpu, is a pain in the ass. The asm code is too ugly.

So Cedric ask for a MMU flag to say to use the same memory layout in tile for CPU and GPU, : you don't need to change pixel place during the copy.

It could be very interresting if memory are shared between gpu and cpu : no copy at all will be needed.

One more question from my part : Is it possible to always do 2D tiling memory layout compatible with GPU, to avoid the flag ? It's only a different way to read the memory.

2015-04-01 1:10 GMT+02:00 <whygee@xxxxxxxxx>:

Le 2015-04-01 00:48, Cedric BAIL a ÃcritÂ:

On Tue, Mar 31, 2015 at 11:57 PM, <whygee@xxxxxxxxx> wrote:

I seem to remember that the RPi's Broadcom chip has several DMA channels,
including one with "2D" capability, it might do what you seem to describe.
It takes strips of equal sizes from one memory, and puts them with different
spacings or strides somewhere else. Is that what you think of ?

Not really. It would help for the case of DMA from/to the GPU, but not
for all the 2D rendering case you could do on the CPU.

Could you write an elaborate document about it, like a sort of report ?
I'm confused again and a few diagrams will help me :-)

yg

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