Le 2015-04-01 09:19, Nicolas Boulay a ÃcritÂ:
GPUÂ use a specific memory layout "in Z" to favor locality access and caching. This is simple "tiling". When you copy this kind of image between cpu and gpu memory, the pixel must be moved to the right place. And it's slow. Tiling is a good also for cpu code on image. Using tiling "by hand" in cpu, is a pain in the ass. The asm code is too ugly. So Cedric ask for a MMU flag to say to use the same memory layout in tile for CPU and GPU, : you don't need to change pixel place during the copy. It could be very interresting if memory are shared between gpu and cpu : no copy at all will be needed. One more question from my part : Is it possible to always do 2D tiling memory layout compatible with GPU, to avoid the flag ? It's only a different way to read the memory.
Hi,you both use terms that have different meanings depending on the context.
"in Z" could be about the Z-buffer. and none of you has mentioned the "size" of the "tiles". Cedric used the term "MMU" which is traditionally used for protection and remapping of 4KB blocks, which is a totally different beast from the pixels. Cedric has posted a link that says that bytes are interleaved, and it crosses raster line boundaries. It's not very easy to do. The document also mentions different interleaving patterns so it's not possible to do a one-fits-all unit sitting on the bus for this. I believe that your solution is a SIMD instruction that performs "byte shuffling". I've seen it appear in big CPUs years ago. Why isn't it used for this purpose ? yg ************************************************************* To unsubscribe, send an e-mail to majordomo@xxxxxxxx with unsubscribe f-cpu in the body. http://f-cpu.seul.org/