[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [f-cpu] Register Bank



On Sat, 4 Aug 2001, Ben Franchuk wrote:

> > Non maskable interrupt! Definitely not a reset. At least
> > I don't know of any processor having two resets :-)
> > The NMI usually is used for very high speed reaction on
> > external events that must be reacted on. Therefore it is
> > not maskable. But it's just another interrupt still.
> 
> The whole idea behind two resets deals with the complexity
> of the system. I was thinking reset #1 - hard reset - resets the
> entire system and cpu's. A second reset would be like a NMI
> but just clears only a few specific internal locations to put it into a
> known state  for a single thread with bad or damaged code segment.
> If you have a cpu controlling a rocket in space - three redundant cpu's
> and one goes down from radiation you would just want to reset the one cpu
> and still have the other two continue running. You don't want to reset
> all 3 and crash the rocket!. Ben. 

Yeah, I love that kind of system design. To be honest,
NEVER would I combine these 3 cpus with the same reset
signals. They would have to be loosely coupled. Only in
this case one ends up with 3 systems running in parallel
with minimal sideeffects. The data exchange is done by
communication to even get the power lines independent
from each other. :-)

JG

*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/