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Re: [f-cpu] Register Bank



hi !

Ben Franchuk wrote:
> Juergen Goeritz wrote:
> > On Fri, 3 Aug 2001, Ben Franchuk wrote:
> > > Juergen Goeritz wrote:
> > > > On Fri, 3 Aug 2001, Ben Franchuk wrote:
> > > > > Juergen Goeritz wrote:

<snip !>
> > Non maskable interrupt! Definitely not a reset. At least
> > I don't know of any processor having two resets :-)
> > The NMI usually is used for very high speed reaction on
> > external events that must be reacted on. Therefore it is
> > not maskable. But it's just another interrupt still.
> 
> The whole idea behind two resets deals with the complexity
> of the system. I was thinking reset #1 - hard reset - resets the
> entire system and cpu's. A second reset would be like a NMI
> but just clears only a few specific internal locations to put it into a
> known state  for a single thread with bad or damaged code segment.
> If you have a cpu controlling a rocket in space - three redundant cpu's
> and one goes down from radiation you would just want to reset the one cpu
> and still have the other two continue running. You don't want to reset
> all 3 and crash the rocket!. Ben.

so it is more about the reach of the reset signal. ie: reset another
CPU without resetting oneself. when this is put this way, it becomes clear
how to implement it.

WHYGEE
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