Re: [f-cpu] Verilog vs. VHDL Discussio Archive?

[Juergen Goeritz <goeritz@oekomm.de>]

Hi,

let me add a comment too.

VHDL is a tool independent language that also was
standardized more than 10 years ago and managed to
let hardware be designed in a software like manner.
It's also independent of the backend synthesizer
one chooses. Verilog is less tool independent but
it already existed earlier and that may be why it's
still in use.

I prefer neither of both. They both lack a good means
of table input for statemachines and decoders. I do
not see what's going on in the logic at the first glance.
Therefore it's hard to read and write and thus wastes a
lot of precious time. ;-)

JG

On Mon, 6 Aug 2001, Yann Guidon wrote:
> > Is there a summary somewhere of why VHDL was picked over Verilog? I know
> > there was a religious discussion about that, and I do not wish to restart
> > it... I'd just like to read it somewhere.
> 
> as far as i remember...
> 
> nobody died from this war, fortunately :-) yet the question was raised long ago.
> 
> one big bias is that a lot of contributors are in Europe. hence the VHDL,
> because it is taught in schools.
> The other bias is that the first files were written in VHDL.
> The last one is that there is not much people here who understand
> "real" CPU designs and how to make a circuit, and this little number
> once choosed to use VHDL. Concerning the development "team", i can count
> Nicolas, Michael and me, so the question was not a real problem
> (we mostly are in France and Germany).
> 
> As a consequence, we have been searching tools for a long time,
> some can even access "commercial class" tools.
> 
> however, nothing keeps anyone from translating to Verilog.
> as long as it is fully documented ;-P
> 
> > Thanks,
> > -- Hiten
> WHYGEE
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