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Re: [f-cpu] register set BIST



hi :-)

Juergen Goeritz wrote:
> Hi Yann,
> 
> On Tue, 7 Aug 2001, Yann Guidon wrote:
> > coding in C is getting very frustrating and i would like to do some
> > more VHDL, if possible with a synthesiser behind... but i can't
> > have all that on my laptop :-)
> 
> Why are you getting frustrated about your code?

-1) i don't like C
-2) i don't have VHDL on my laptop
-3) i have too many problems to solve before i can really switch to VHDL-only.
-and a lot of other stuffs.

> > back to the BIST : i do not test (yet) both write ports
> > (only one, maybe the second if we duplicate the BIST)
> > or the individual write enables. However, within a few thousand
> > of cycles, my method can check any fault that occurs in the
> > 64*63=4032 bits of the bank.
> 
> Yes, have programmed some of these by myself. But to do it
> in software one first have to verify the instruction decode
> and execution phase is working. The address decoding of the
> registers must also be verified, i.e. one needs a test that
> will run for half of the registers in parallel with different
> data in each register at a single time stamp. One half doing
> the '0' shuffle, the other the '1' shuffle and vice versa, e.g.
> 
> 0x0000 0000 0000 0000     0xffff ffff ffff ffff
> 0x0000 0000 0000 0001     0xffff ffff ffff fffe
> 0x0000 0000 0000 0002     0xffff ffff ffff fffd
> ..                       ...
> 
> But it could also be done on a 8bit or 16bit or 32bit base.
> Afterwards you are sure that every register bit can hold
> the '0' and '1' value and the bits are independent from
> each other. If you don't use the same values for all the
> registers at the same time, you have implicitely checked
> the adress decoding of the registers, too.

I did that even better in the BIST that you will find in
the latest snapshot i sent. it requires 26 passes, each
requiring a full write and read of all the registers, hence
26*2*63=3276 clock cycles. it could be shortened with some
pipelining but the general BIST strategy is not fully defined.


I think that i will reserve special Xbar ports (servce doors)
for doing the BIST throughout the circuit. It's very practical
because we don't need much more wires to propagate the data,
we test the Xbar at the same time, and there's no need of
boundary-scan integrated inside the pipeline flip-flops
(at least, the requirement is reduced a lot). It is also
very fast because it is done with full-speed data and not
1/200th speed, thanks to the parallelism allowed by the buses.


currently, the register set is BISTed directly (direct connexion
of the BIST FSM). but when it is ready, i'll design the Xbar and
move the BIST behind a Xbar port. With some multiplexing, we can
add other BIST machines for each additional unit.

what do you think ?

> JG
WHYGEE
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