[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [f-cpu] Re: FC0 XBAR



hi !

nicO wrote:
> Yann Guidon a écrit :
<snip>
> > When the instruction arrives 1 cycle too late for the Xbar bypass,
> > it is not possible to issue it, because the Register cycle
> > requires 1 cycle to update. Emitting it without proper measures
> > would be a catastrophe.
> >
> > There are 2 solutions : either delay the instruction or add another
> > small bypass. I think that i found the solution for the bypass :
> > it's just another register, and we have to insert a few MUX entries
> > in the Xbar-read part.
> >
> 
> Hum, strange, it became to look like my own bypass/variable latency
> system... ;p Be carefull whygee you will seem to be okay with me !

maybe, maybe not.
in fact, the data in question is already latched at the output of the
Xbar_write_port (or the input of the register set, depending on where
you watch). so there is no need to "really" add the latch,
"only" a few wires :-P and some MUX inputs.
it has nothing to do with your "original idea" because yours does not
solve this particular problem.

> nicO
WHYGEE
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/