Re: [f-cpu] Register Bank

[Yann Guidon <whygee@f-cpu.org>]

Juergen Goeritz wrote:
> 
> On Tue, 7 Aug 2001, Yann Guidon wrote:
> > > > basicly, the register set is split into 5 "banks" with individual
> > > > write enables. what is even more difficult is how to handle the
> > > > flags in parallel. The reason is that i have not practiced VHDL
> > > > for a long time :-/
> > >
> > > How comes that you use '5' banks? I remember the number of
> > > registers to be 2^n even. 32/5 doesn't fit, 64/5 doesn't fit
> > > either. I am a bit puzzled now. :?)
> >
> > that's a "side effect" of using both partial writes for "normal"
> > data and loadcons instructions :
> >  the first one writes in 8, 16, 32 and 64-bit versions,
> >  loadcons writes 16-bit data after a shift of 0, 16, 32, or 48 bits.
> > The union of these fields gives :
> >  0-7, 8-15, 16-31, 32-47, 48-63
> Aha, a split in the width at different sizes. Interesting!

maybe yes, maybe not, it's "simply" a consequence of that fact that
2 kinds of instructions can write at different boundaries.

to make things clearer, here is an extract from an old version
of the QDCPOC :

UMAX mask_LUT[] = {
  0x00000000000000FFLL, /*  8-bit write mask */
  0x000000000000FFFFLL, /* 16-bit write mask */
  0x00000000FFFFFFFFLL, /* 32-bit write mask */
  0xFFFFFFFFFFFFFFFFLL, /* 64-bit write mask (SIMD) */
  0x000000000000FFFFLL, /* LOADCONS */    /* degenerate */
  0x00000000FFFF0000LL,
  0x0000FFFF00000000LL,
  0xFFFF000000000000LL,
  0xFFFFFFFFFFFFFFFFLL, /* LOADCONSX */   /* degenerate */
  0xFFFFFFFFFFFF0000LL,
  0xFFFFFFFF00000000LL,
  0xFFFF000000000000LL                    /* degenerate */
};

it shows the fields that are updated under which circumstance.
now, i have "split" the register bank and i don't use this code,
i have only a 5-bit field (one bit "enables" one bank) that comes
from the scheduler's queue.

> JG
WHYGEE
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