Re: (m) Re: [f-cpu] More Instruction Set Trouble

[nicO <nicolas.boulay@ifrance.com>]

Yann Guidon a écrit :
> 
> hi,
> 
> nicO wrote:
> > Michael Riepe a écrit :
> > > On Sat, Aug 18, 2001 at 10:09:39PM -0400, Lee Salzman wrote:
> > > [...]
> > > > >Any other ideas how we can reduce/avoid the `address load penalty'?
> > > > An add coupled with a prefetch for data address loads off a
> > > > base/module register would be very nice. Possibly an immediate add
> > > > that some how supported longer immediate constants would be nice too,
> > > > but that could be done without.
> > > The `address add' idea looks better and better, and it's good for
> > > pointer/array/structure accesses, too.
> > Hum i don't like that at all because you schould put an adder just
> > before the memory unit. So we just as to make the pipeline longer. One
> > of the key point of the FC0, to shorten the pipeline, is to put in
> > parrallele the ALU and the load&store unit. If we put it in serial, we
> > longer the pipe. So i think, it's much better for that case to use 2
> > instructions. Never forget that it's adding an other addressing mode .
> 
> my personal point of view is to simply add a new "flavour" of the
> loadaddr instruction, which doesn't use the PC, that's all.
> 
> The current form of LOADADDR looks like this : (from the manual)
> 
> LOAD a relative ADDRess to a register
>  loadaddr r2, r1
>  loadaddrd r2, r1
> r1 = PC + 4 + r2, check the result in the D/I TLB and eventually prefetch the data.
> 
> If you add a new opcode which says that we don't use PC but r3
> (it's fairly straight-forward),  we're done. no curious scheduling,
> nothing to change, the necessary HW doesn't change and we must simply
> update the manual and the instruction encoders/decoders.
> 

Seems ok to me. But why don't we map the PC inside the register map ? 

nicO

> > nicO
> WHYGEE
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