Hi Juergen
Thank you for the questions.
Post your mailing address and I will send you a
copy of my presention Handout.
Reference your other questions
1. Is the
design only relating to SSRAMs with full decoding?
Please explain further - I don't understand your
question.
2. Maybe it
is based on a 24 bit original design?
No. The DDP-516 was a 16 bit Minicomputer. The
Software that I am
going to capture is written for that processor -
all 9,967 Instructions --------------------this portion is the Language
Processor. A DDP-416, also 16 Bit; was
used as a Peripheral Processor. The 416 had a reduced
instruction set.
But otherwise identical to the 516. I intend to move
Disk Processing
from the Language to the Peripheral. The two will
comunicate with each-
other via Interprocessor Interrupt with a Mailbox in Global
Memory.
The basic system can service up to 128
User Terminals; anything
more than 128 - will have to communicate via Inter-System
Interrupt.
All Hard Disk operations will be handled with one Peripheral
Processor
being designated as System Master. He also communicates
with other
standard peripheral devices such as, Printers, Modems, FAX,
Real Time
Clock, you name it.
3.
Could you explain why you use a 72 bit design?
The 72
Bits are for Instructions and all Data is 32 bit. Frankly, I
pursue
all logic design with micropramming in my mind. It
simplifies the design
of control functions. For example; the Floating Point
design I worked on
at Honeywell Information Systems had a 108 Bit Micro
Instruction. My
management never directed me with any constraints - make it
WORK.
I DID.
In this design I ended up with One Bit for each Class of
Instructions; with
a 4-bit Field used for decoding one of 15 possible
instructions. An all
zero's fetch is used for the NOP instruction which occupies
program
space - but has zero execution time. This will come in
handy later in the
program process. You must also understand - there is
basically only one
on chip register and that is a 32 Bit Accumulator. I
also have implemented
128 Index Registers - one for each User. I hope they
aren't used as it
adds to the execution time. The 18 bits should be used for
all Direct
Operations if possible. I also have an Indirect
Addressing Mode. This too
will add to execution time. The instruction also
contains four bits to
timing - very useful for massage purposes.
All direct JMP & JST (jump and store return) instructions
ooccupy program
space but have ZERO execution time. There are currently
2,082 of these
out of the 9,967. This will undoubtedly change as I
found several places
in the code where Instruction Modification was used, and was
permitted
in that period of time. Will also have to consider Data
- will change from
two bytes to four bytes.
Historically, Registers of varying numbers were added to the
hardware
due to the cost of relatively slow Core Memory. I can
now access CMOS
memory just as fast as I can an on-chip Register File.
And I can now have
thousands of so-called registers.
Hope this answers your questions. Don't
hesitate to ask more.......
Regards
Dick Hartney
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