[f-cpu] condition checking and register atribote cache

[jaap stolk <jwstolk@yahoo.com>]

hi,

im trying to add conditional instructions to
fcpusim, and have some ideas:

according to the manual there will be "cache" copy
of the flags, because reading a register is
rather "slow".

what i would like to do is use the x-bar read-bus
instead. this is possible, because the condition
register is read onto the x-bar (but not passed on to
any EU)
if the condition is false, we can simply disable the
clock signal that clocks the data and control
signals from the x-bar onto the EU's
(just like if there is a stall)
and disable the clock signal that clocks the port
numbers into the x-bar write queue.
(just like if there is a stall)

this will automatically fix the bypassing problem in
situations like these:

move    r2,r3
nop
move r3,r4,r5 ( if (r3) r5-r4; )

it seems to be ok for normal instructions and register
move instructions, i'm not sure how it will go
with conditional moves, loadcons. etc.

dous this sounds reasonable, or are there any
major problems i overlooked ?

i also made a drawing of the write queue / scheduler.
i'll upload it if anyone is interested.

jaap.


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