Re: Rep:Re: [f-cpu] Manual 0.2.6

[Michael Riepe <michael@stud.uni-hannover.de>]

On Fri, Aug 02, 2002 at 12:46:28PM +0000, Nicolas Boulay wrote:
[...]
> > >         cshiftl r3, r2, r1      // r1 = r2 << (64 * r3)
> > >         cshiftr r3, r2, r1      // r1 = r2 >> (64 * r3)
> > > 
> > > This can probably be integrated with the SHL execution unit.
> > 
> > Why not using the SIMD flag ? And do :
> >  r1 = r2 << ([8|16|32|64]*r3)
> 
> Too complicated.
> 
> >>> From hardware point of view ? You need in fact 4 shifters. I beleive
> such shifter are smaller than a true 64 bits one.
> Maybe the 16 bits version could be implemented (sizeof the loadcons).

I don't want to make the control logic too complex. Therefore, the basic
shift count (= chunk size) will have to be fixed. If it were variable,
I also had to scale (that is, shift) the second operand in front of the
control logic part.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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