Re: [f-cpu] Conditionnal load and store, the return

["Christophe Avoinne" <christophe.avoinne@laposte.net>]

Back from vacation. Wooh not less than 2000 emails received !!

----- Original Message -----
From: "cedric" <cedric.bail@free.fr>
To: <f-cpu@seul.org>
Sent: Sunday, August 04, 2002 9:45 PM
Subject: [f-cpu] Conditionnal load and store, the return


> Hi,
>
> I have reread the discussion about conditionnal load and store, and I
think
> that we forgot something : exception. In fact when we do a load or a store
> and check the condition only on write.

Spoken about the bit in a LSU0 entry telling us if we can write ? if it is
like a write-right token, setting it to 1 allows the first one to reset it
and have right to write. If an exception occurs at this place, it means that
there is no matching LSU0 entry (am I wrong ?), so there is no right to
write and condition fails. Meanwhile, the exception is executed. At
exception exit, condition fails so we can reexecute the faulty conditional
store instruction.

> The problem is what append if page
> fault occur ? I think we must clarify that.
> From my point of view I think that we must do the test before starting any
> memory operation, so a trap only occur if the test is true. We must do the
> same if we have a conditionnal prefetch. It's for me the only way to
> correctly execute the 2 branch of a if simultaneously.
>
> Finally what did we do with the cachemm instruction ? Did we remove or
change
> this strange instruction ?
>
> Cedric
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