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Re: [f-cpu] F-CPU endianess...


Nikolai Dimitrov wrote:

Hi again people,

Can you help me to clear this situation... We have several
bytes memory, starting at address 0x00.

address           : data
0x0000000000000000: 0x1122334455667788
0x0000000000000008: 0x99AABBCCDDEEFF00

data in BE representation:
msb             lsb

So, if we have Big Endian F-CPU, memory will be read like
read_be8  (0x00) = 0x88
read_be16 (0x00) = 0x7788
read_be32 (0x00) = 0x55667788
read_be64 (0x00) = 0x1122334455667788

data in LE representation:
lsb             msb

....and, if we have Little Endian F-CPU, memory will be read
like this:
read_le8  (0x00) = 0x11
read_le16 (0x00) = 0x1122
read_le32 (0x00) = 0x11223344
read_le64 (0x00) = 0x1122334455667788

IMHO this means that right 5 bits from core address bus are
disconnected, and
core cannot address data at locationa other than multiples
of bus widht (2^5 = 64)?
So access to these locations can be done only by reading
memory with narrowest data type,
capable of extracting needed data? I don't think this is a
problem, I'm only asking if I correctly realized the memory
access operations of the core... I know, that core must
support both data representations...

The core is "decoupled" from the external memory with the help
of the LSU (Load/Store Unit) and the Fetcher (that feeds the decoder with
instructions). The endianness is modified in the LSU, with a kind of integrated shift register
(not exactly this way, but this helps to understand).

So : the core sees whatever address it wants, with whatever granularity (BUT it must be aligned).
The LSU does the job, and provides BE or LE according to the instruction word.

it's both simple (for the programmer) and complex (for the HW design) but at least,
there are no chances to hit a patent :-)


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