[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]

[f-cpu] F-CPU endianess...

Hi again people,

Can you help me to clear this situation... We have several
bytes memory, starting at address 0x00.

address           : data
0x0000000000000000: 0x1122334455667788
0x0000000000000008: 0x99AABBCCDDEEFF00

data in BE representation:
msb             lsb

So, if we have Big Endian F-CPU, memory will be read like
read_be8  (0x00) = 0x88
read_be16 (0x00) = 0x7788
read_be32 (0x00) = 0x55667788
read_be64 (0x00) = 0x1122334455667788

data in LE representation:
lsb             msb

...and, if we have Little Endian F-CPU, memory will be read
like this:
read_le8  (0x00) = 0x11
read_le16 (0x00) = 0x1122
read_le32 (0x00) = 0x11223344
read_le64 (0x00) = 0x1122334455667788

IMHO this means that right 5 bits from core address bus are
disconnected, and
core cannot address data at locationa other than multiples
of bus widht (2^5 = 64)?
So access to these locations can be done only by reading
memory with narrowest data type,
capable of extracting needed data? I don't think this is a
problem, I'm only asking if I correctly realized the memory
access operations of the core... I know, that core must
support both data representations...

Безплатната поща в mail.bg вече е 1GB!

To unsubscribe, send an e-mail to majordomo@xxxxxxxx with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/