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Re: [f-cpu] F-CPU architecture...


Nikolai Dimitrov wrote:

I'm not cpu architecture expert, only amateur. I once
thought about the apropriate architecture about a desktop
and embedded procesor. Before a couple of years I developer
over a dozen of industrial boards with Microchip pic RISC
controllers, and decided that it's very good to have
simultaneously access to instruction memory and data memory
in one cycle. But... The instruction memory was filled with
code for execution, and read-only, so you program the
instruction memory once, and the program is executed, and
data memory is only for variable data... I think this is
not apropriate for a desktop workstation (I hate the word
pc...), because here programs and data are all placed in a
R/W memory, so you can load lost of different programs and
execute them. This means that Von Neumann is may be more


But, looking at OpenRISC design, and thinking
again for this problem, I asked myself - can be connected
both instruction and data busses from the core to the one
and only memory bus, and the core to use I-cache and
D-cache to read and write data to main memory a'la Von
Neumann, but actually the core will be Harvard (with 2
buses - instruction and data). These are only my personal

Actually, that's what most processors do nowadays. Code and data have separate caches and go separate ways inside the core. But on the outside, two separate memory buses for code and data don't make sense. In particular since you would waste a lot of I/O pins.

Michael "Tired" Riepe <michael@xxxxxxxx>
X-Tired: Each morning I get up I die a little
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