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Re: [f-cpu] F-CPU architecture...
Michael Riepe wrote:
Bogdan Petrisor wrote:
Well the question about Harvard architecture was just a ... question.
I was curious if this was
considered sometimes during the developement of the F-CPU (and yes I
have read the manual at least
and found no
reference about it). I think it can offer a bit more performance and
since I remembered that the
ELF format is already separated in data segments and instruction
segments for a moment seemed a
Well, not really. It's true that ELF files contain one or more
segments, but they're not separated in code and data but in writable
and read-only data (where instructions usually reside in a
non-writable data segment). And even read-only segments may be written
to during program loading and dynamic linking, e.g. to apply relocations.
Harvard architecture is nice for special purpose machines, DSPs and such.
This is also used for some microcontrollers like Microchip's PICs
(that i use a lot, from the 16LF877 at
to the ultrasmall 10F20x in SOT23). And these architectures count as
F-CPU is meant to be "general".
But you can't run a decent operating system on them - how are you
going to compile and load a program if you can't write to your program
memory space? Programs must be pre-installed or loaded from outside,
preferably while the CPU is not running. It's a little like a BIOS
Most DSP (and i know ADi's quite well) manage to access PM and DM on a
unique external bus that
shares several addressing spaces. But that's far from ... flexible.
We will probably integrate a separate read-only "program memory" for
the built-in self test (BIST) that runs after power-up - I guess that
will be too hard and too costly to hard-wire. But the rest of the
instruction stream will come from main memory.
ROM is probably useless.
First reason : FC0 will certainly "live" as a FPGA in the beginning,
so no need to make exhaustive failure verification.
Second reason : i had found, years ago, how to create the BIST
using a FMS (some hundred thousand cycles are enough, the key
is to find in which order to send signals through the pipeline).
Third reason : RAM is better and cheaper.
And I think that bootstrapping the CPU with the help of an external,
cheap microcontroller is a good help.
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