[f-cpu] F-CPU fetch unit

[Bogdan Petrisor <petrisorbogdan@xxxxxxxxx>]

--- Yann Guidon <whygee@xxxxxxxxx> wrote:

> stop !  the PC is not a real register.
> in fact, there is no PC. It is just provided as an artifact
> for old-school programming.
> 
> "PC" is just a read-only port as seen from the Xbar.
> it is "built" at every cycle by the Fetcher, which concatenates
> several internal fields and counters. that's all.
> The PC is "advanced" simply because the running counters
> are incremented to (speculatively) provide new instructions to
> the instruction decoder.
> 

ok, so the PC (let's call it like this but we're reffering to the RO port of the Xbar) must have
the width of the other regiters that are connected to the Xbar. that would make for now 64 (a
configurable constant from what I've seen in the source files). This PC is an output from the
fetcher. But how does the jump works then? Is the instruction decoded here instead of the decoder?

> - The Fetcher SPECULATIVELY fetches instructions from the L1 I-cache and 
> from outside memory in case of a miss.
> - The Fetcher is composed of several "lines" (say, 8 for a start). These 
> are a sort of "cache" for the L1 cache,
> but with many ports (read ports go to the decoder and I-L1, write ports 
> are fed by the external memory and the L1).
> - Each line contains a field that says if the translation is OK, and an 
> additional field contains the "virtual address"s MSB
> (so that the PC can be rebuilt)
>  - there is also a flag that says the size of the page. It is used both 
> for rebuilding the PC and to trigger a TLB lookup
> when the internal counter overflows (we have to know which of the 
> counter'sbit will trigger the lookup).
> 

so you mean like 8 little fethchers and while one of them puts the current instruction out the
others get more instructions from the cache?
So when a miss finnaly happens the fetcher gets ony the guilty instruction from the RAM or is it
responsible for the replacement of the pages in cache?

> You see, it is quite complex, the function arises from the collaboration 
> of several specialised units,
> rather than a single "black box" (that's why the term "MMU" is not 
> suitable at all).
> And developping the Fetcher+LSU+TLB+Cache memory system is not as easy 
> as creating
> an execution unit, because there are a LOT of side effects.
> 

yes, I (usually) love problems :D:D. The reason I'm asking this is because I like to have a
general ideea about the ports before staring to work on a block/entity/unit/whatever you like to
call it.

--------------------------------
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Fear is the little-death that brings total obliteration.
I will face my fear.
I will permit it to pass over me and through me.
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Where the fear has gone there will be nothing.
Only I will remain.
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