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Re: [f-cpu] F-CPU architecture...
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- Subject: Re: [f-cpu] F-CPU architecture...
- From: Bogdan Petrisor <petrisorbogdan@xxxxxxxxx>
- Date: Mon, 29 Aug 2005 19:22:41 -0700 (PDT)
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--- Yann Guidon <whygee@xxxxxxxxx> wrote:
> Then we can go on : first, dust off the vital files (VHDL and other
> source code)
> and then update the manual.
Hey, count me in for that. I've always hated PDF (except for resumees). If you want me to convert
the bloody manual to HTML just say so :D:D
Now if I can divert a bit your attention to more boring questions. As fas as I understand from the
manual F-CPU uses virtual adresses right? Since the PC is 64 bits(just like a noral register) and
the pases can have several sizes (4 KiB, 32 KiB, 256 KiB and 2048 KiB .. page 42 of the manual) am
I right to assume that 21 bits will be used for offset (the lower ones) and the rest 43 bits for
Also from the same page: "The internal TLBs are software-controlled through a set of Special
Registers. No microcode or hardware mechanism is foreseen that will help search a page table entry
in memory. An OS exception is triggered whenever a task issues an instruction that access a memory
location that is not in the internal Page Table (TLB)."
So then basically the fetch unit must get the instruction from ICache and trow and exception when
it doesn't find the page. Right?
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