Hi!
Bogdan Petrisor wrote:
Now if I can divert a bit your attention to more boring questions. As fas as I understand from the
manual F-CPU uses virtual adresses right? Since the PC is 64 bits(just like a noral register) and the pases can have several sizes (4 KiB, 32 KiB, 256 KiB and 2048 KiB .. page 42 of the manual) am
I right to assume that 21 bits will be used for offset (the lower ones) and the rest 43 bits for
page?
Also from the same page: "The internal TLBs are software-controlled through a set of Special Registers. No microcode or hardware mechanism is foreseen that will help search a page table entry in memory. An OS exception is triggered whenever a task issues an instruction that access a memory location that is not in the internal Page Table (TLB)." So then basically the fetch unit must get the instruction from ICache and trow and exception when it doesn't find the page. Right?
-- Michael "Tired" Riepe <michael@xxxxxxxx> X-Tired: Each morning I get up I die a little ************************************************************* To unsubscribe, send an e-mail to majordomo@xxxxxxxx with unsubscribe f-cpu in the body. http://f-cpu.seul.org/