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Re: [f-cpu] F-CPU architecture...


Bogdan Petrisor wrote:

Now if I can divert a bit your attention to more boring questions. As fas as I understand from the
manual F-CPU uses virtual adresses right? Since the PC is 64 bits(just like a noral register) and the pases can have several sizes (4 KiB, 32 KiB, 256 KiB and 2048 KiB .. page 42 of the manual) am
I right to assume that 21 bits will be used for offset (the lower ones) and the rest 43 bits for

The PC is _at_least_ 64 bits. And log2(pagesize) of them will be used for the offset.

Also from the same page: "The internal TLBs are software-controlled through a set of Special
Registers. No microcode or hardware mechanism is foreseen that will help search a page table entry
in memory. An OS exception is triggered whenever a task issues an instruction that access a memory
location that is not in the internal Page Table (TLB)."
So then basically the fetch unit must get the instruction from ICache and trow and exception when
it doesn't find the page. Right?

Almost. When the instruction is not in the cache, it will be loaded from memory automatically. But if the virtual address is not listed in the TLB (= not mapped to physical RAM), a trap is raised.

Michael "Tired" Riepe <michael@xxxxxxxx>
X-Tired: Each morning I get up I die a little
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