Re: [f-cpu] FC0's RTL scheduler

[Yann Guidon <whygee@f-cpu.org>]

hi !

Michael Riepe wrote:
> On Mon, Dec 17, 2001 at 06:48:44PM +0100, Yann Guidon wrote:
> > while trying to cleanup my source tree,
> > i saw that i couldn't make anything work :-)
> Shit happens :)
but why to me ? :-)

> > otherwise i have to move files around,
> > modify configurations, check that everything
> > is ok... too much work for my sick brain.
> > So, i'm finally biting the first files
> > that describe the scheduler/decoder/issue stages.
> > i'm only sketching the first outlines now
> > and i try to to fall too much into very low-level
> > things... wish me luck !
> You mean, you try NOT to fall?
yup, 'xcuz,

>  Good luck, then.
it seem to work :-)
well, i am just writing stuff without much testing,
but the overall structure is not too difficult :
i think that i can make it. Using RTL description
is not so difficult compared to behavioural
because there are a lot of parallel things that
are going on. Writing the QDCPOC this summer has
helped me, but i finally prefer to use VHDL :-)))

> > I see that we have most EUs going on or done
> > so this is the best place to work. However i still
> > have to figure how many output ports the IMU has.
> Eight -- two for each chunk size (holding the high and low parts of
> the double-width product). We have to reorder the result bits for the
> original macl/mach instructions, however.
can you be more precise ?

does that mean that :
 8-bits   -> 2 cycles
 16-bits  -> 4 cycles
 32-bits  -> 6 cycles
 64-bits  -> 8 cycles
plus an additional cycle for mach/macl ?

Thanks for the answer,
>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
WHYGEE
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