[f-cpu] Synthesis Results

[Josh Fender <fender@ecf.utoronto.ca>]

Hi,
  Sorry about the slow results on the synthesized speed results but the
system I use to synthesize has been very busy.  I successfully synthesized
both the eu_asu and the eu_shl, although it was more difficult then YG ROP
unit.  Some of the pragma statments had to be removed for synplicity to
compile the VHDL files, but other then this change, the VHDL code compiled
without difficulty.

  The timing results were a little more difficult to deal with.  The
shuffler unit reported in the neighbourhood of 40MHz.  This number can be
directly compared with my previous results for the ROP unit.  The Adder
results were not as clear cut.  Due to the use of clocks on some signals,
and not on others, my timing tool found several clock paths.  These paths
had timings between 10-40MHz.  These numbers mean very little as I did not
have the time to examine the vhdl files in detail to understand the
different clocking methods.

  The multiplier was the main cause for my delays.  I needed to find a
timeblock of about 16 hours to synthesize it.  Unfortunately my
synthesizer crashed when it tried to dump the results (after 16 hours) so
I don't have complete information.  What I could extract was that the
synthesizer predicts that the circuit will run at 17MHz.  (I have found
this number is accurate for most circuits assuming the FPGA isn't to
congested).  And from examining the EDF output file it appears that the
multiplier uses > 30000 4 input LUTS.  Obviously this multiplier is too
big for an affordable FPGA implementation.  A reasonable speed grade of an
FPGA this big will run around $2000US.  Overall I didn't learn much about
the multiplier.

  To get more accurate results input and output registers for all signals
need to be added and the EU resynthesized.  Perhaps if I find more time in
the future I will attempt it, but for now I am too busy.

- Josh Fender




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