Re: [f-cpu] correction : no delay required for the multiplier

[Yann Guidon <whygee@f-cpu.org>]

hi !

Michael Riepe wrote:
> On Sat, Dec 22, 2001 at 04:08:44AM +0100, Yann Guidon wrote:
<snip>
> > In the scheduler FIFO, i have two columns of N positions
> > (N-deep FIFO) with each the following informations :
> >   - valid           (1 bit)
> >   - register number (6 bits)      -> used during the register write cycle
> >   - write mask      (2 bits)      -> used during the register write cycle
> >   - write port      (3 or 4 bits) -> used during the Xbar cycle to select the data
> > Each FIFO stage contains (for most bits) a register (that is clocked
> > by the main clock), a few comparators (for the register numbers)
> > and a MUX that selects either the previous stage's data OR the data coming
> > from the decoder's LUT.
<snip>
> It's crystal clear :)  And it looks good to me.  I would probably
> store a pre-decoded write mask (5 bits) instead, but that's a minor
> issue.
it is minor, and in fact only 2 bits are necessary.
the other bits are added at the bottom of the FIFO because
no "regular" operation writes to a specific 16-bit chunk.
The added bits are needed _only_ for the loadimm instructions,
which do not need to go through all the FIFO (they take only 2 cycles).

<snip>

WHYGEE
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