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[f-cpu] signed cmpl
- To: <f-cpu@seul.org>
- Subject: [f-cpu] signed cmpl
- From: devik <devik@cdi.cz>
- Date: Mon, 16 Dec 2002 10:41:00 +0100 (CET)
- Delivered-to: archiver@seul.org
- Delivered-to: f-cpu-outgoing@seul.org
- Delivered-to: f-cpu@seul.org
- Delivery-date: Mon, 16 Dec 2002 06:12:02 -0500
- Reply-to: f-cpu@seul.org
- Sender: owner-f-cpu@seul.org
Hi,
when I was adding conditionals into gcc code I found
that signed compare is often used by gcc backend
(more than unsigned one for most of code).
IMHO the signed compare can be (even for SIMD) done as:
xor.N a0,a1,t0 // get sign difference
cmpl[e].N a0,a1,t1 // unsigned compare
shiftari.N N-1,t0,t0 // convert MSB bit to negation mask
// free slot here
xor.N t0,t1,t0 // negate result for different signs
it is 6 cycle latency! Can some HW guy here tell whether can
I count on signed cmp being computed by INC unit too ? It
would be one xor gate in its critical path AFAIK (negate
result if sign bits were different).
It it would not fit into INC unit I'd suggest to implement
signed compare instead of unsigned - it is more often used
and 32 bit unsigned cmp can be then done by zero_extending
operands (it is at no cost in fcpu) and perform 64 bit signed
cmp instead. The resulting 0xfff... pattern will be twice
long but for subsequent jmp it doesn't matter.
devik
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