Guy's & Girls
In my design of the
Erin32/64/ALP76 I register the result which is Equal to,
Greater Than, or Less Than. These results stay
registered until another CMP is
issued. I then use a Test & Branch
instruction for discrete test. The design is
based on the SN7485 comparator chip.
Other news.
Quicklogic has deleted the only package size in
which all of my designs were targeted. So, I have purchased the ACTEL
design package and will now target my design to the AX2000 which is their
largest FPGA. In the ALP76; the Instruction and Operand Pipeline will be
increased from the current 4 to 16 because the on-chip RAM bits will
permit. Added Indexing to Load/Store Operands from Off-chip Local
Memory.
Also added the LDB (Load Byte), STB (Store Byte),
Multiply, and Divided Instructions.
Arbitration iis required for
Local Memory useage for both Reads and Writes. And with the larger logic
being available I will be able to arbitrate to the specific Memory Block ( 1 of
8 ). I still will use the Cypress Quad and Dual port SSRAM's.
Will now use 39 (Thirty Nine)
ALP76 processors (A Language Processor) and 76 is my age.
Anyone wishing more info - send
a Mail.
Dick Hartney
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