Re: [f-cpu] FPU Adder....

[Nicolas Boulay <nico@seul.org>]

sorry for the stupid copy&paste error.

nicO

Le Mardi 30 Décembre 2003 19:26, Nicolas Boulay a écrit :
> I thing that vhdl standard say that variable can't be view as waveformes.
> MTI/modeltech don't do it either.
>
> 	-- return true is F only have 0
> 	function fl_isnull(F: std_ulogic_vector) return boolean is
> 		variable res : boolean;
> 		variable m   : std_ulogic_vector(1 to F'length) := F;
> 	begin
> 		res := true;
> 		for i in 1 to F'length loop
> 			if m(i) = '1' then
> 				res := false;
> 			end if;
> 		end loop;
> 		return res;
> 	end;
>
> You can't use that.
> 	-- return true is F only have 0
> 	function fl_isnull(F: std_ulogic_vector) return boolean is
> 		variable res : boolean;
> 		variable m   : std_ulogic_vector(1 to F'length) := F;
> 	begin
> 	        res := (F = 0);
> 		return res;
> 	end;
> You could use normal operation. If it don't work translate it to
> std_logic_vector.
>
> Long chain of elsif must absolutly avoided if possible because it's slow.
> Use switch case instead if possible.
>
> "En" signal  must not be in the process sensitivity list of a clocked
> process.
>
<...>
>
>           while (S5MP(MSIZE) /= '1') loop
> 		              S5EP := fl_decr(S5EP);
> 		             	S5MP(MSIZE downto 1) := S5MP(MSIZE-1 downto 0);
> 		             	S5MP(0) := '0';
> 		            end loop;
>
> Dynamic loop can't be synthetised. Synthetiser unroll such loop but can't
> do anything with that. It look like it need a clock but which one ?
> If you want to use loop use only argument that end the loop that can be
> decided at compile time.
>
> nicO
>

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