Re: [f-cpu] register set

[Bruno Bougard <bruno.bougard@imec.be>]

Juergen Goeritz wrote:

> On Tue, 12 Feb 2002, Bruno Bougard wrote:
> > Yann Guidon wrote:
> >
> > > hello,
> > >
> > > the register set is almost finished. I still have to make
> > > an exhaustive testbench and add the zero detector.
> > > I have based the design on transparent latches,
> > > they ensure that the cells are not too large and slow.
> >
> > Ouille ! Please don't do that ! latches are almost not-testable. For FF,
> > you have scan-test.
>
> It's harder to add failsafe approaches later when the storage
> parts have to keep their contence for quite a while and may
> not be clocked again during storage.
>
> > > It's almost completely asynchronous :
> >
> > Ouille 2 : to be avoided as much as possible.
> >
> > > reading is just
> > > combinational (the address is driven by the fetcher's
> > > output register) while writing is driven by the scheduler
> > > queue's output. the write command of each cell is given
> > > by the address decoder ANDed with the write mask,
> > > so writing is allowed when the mask is enabled and the
> > > data remain when the mask goes low. There are certainly
> > > some setup&hold conditions to ensure but it looks interesting.
> > >
> > > Now i'm seeking real implementations and VHDL "wrappers"
> > > of such a bank. I have looked a bit at the latest LEON sources
> > > but they look too messy for me...
> >
> > Generally, optimized register-bank is provided by the technology vendor.
> > I work currently with UMC and I have a RAM/register-bank compiler. This
> > one generate behavioral description for the simulation and a 'blackbox'
> > for the final layout.
> > If you want to see how to implement such a structure efficiently, check
> > e.g WESTE, ESHRAGHAN, Principles of CMOS VLSI design, Addison Wesley.
> > This is also a good book to learn design.
>
> I can remember that they want to stay independent of technology
> vendor libraries and structure compilers that are not freely
> available.

In that case, the best is to write a common interface in which you will
encapsule the module provided by the technology vendor when you will process
the chip. Meanwhile, you can work with a behavioral model that you can write
easily looking at the spec of a 'typical' register bank.

> Also, for what you want to do, a SRAM instance should be more efficient,

> > notably regarding power consumption
>
> Usually you can't read and write in the same clock. You may
> be forced to use multiport SRAM.

just 2-port SRAM which are quite efficient now.

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