Re: [f-cpu] register set

[Juergen Goeritz <goeritz@oekomm.de>]

On Tue, 12 Feb 2002, Bruno Bougard wrote:
> Juergen Goeritz wrote:
> > On Tue, 12 Feb 2002, Bruno Bougard wrote:
> > > Generally, optimized register-bank is provided by the technology vendor.
> > > I work currently with UMC and I have a RAM/register-bank compiler. This
> > > one generate behavioral description for the simulation and a 'blackbox'
> > > for the final layout.
> > > If you want to see how to implement such a structure efficiently, check
> > > e.g WESTE, ESHRAGHAN, Principles of CMOS VLSI design, Addison Wesley.
> > > This is also a good book to learn design.
> >
> > I can remember that they want to stay independent of technology
> > vendor libraries and structure compilers that are not freely
> > available.
> 
> In that case, the best is to write a common interface in which you will
> encapsule the module provided by the technology vendor when you will process
> the chip. Meanwhile, you can work with a behavioral model that you can write
> easily looking at the spec of a 'typical' register bank.

Here we are again. Do we use pre-made modules in our design
or do we use a behavioural description? It reminds me a lot
of the 74xx ttl devices which were formerly used heavily on
PCBs and a lot of hardware guys never quit thinking this way.

I would rather prefer a tool that automatically detects regular
structures in a behavioural model and replaces them during
compilation by vendor type things. But why force the designer
to use this stuff or take care of this stuff by wrappers
already in the design process??? Those tools suck!

Hoops, this is one of the topics that can really make me upset! ;-)

JG

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