Rep:Re: [f-cpu] register set, latches

[<nicolas.boulay@ifrance.com>]

-----Message d'origine-----
De: Yann Guidon <whygee@f-cpu.org>
A: f-cpu@seul.org
Date: 12/02/02
Objet: Re: [f-cpu] register set

hello,
<..>
By the way, if people are "eager" to have a D-ff,
i could probably reuse the dual-edge flip-flop idea
and adapt it a bit...
----
>>>> Dual-edge ???? No, we will use normal cell find
in every technology and not a special thing that
could only be manualy implemented. Please, think only
on rising edge D-flipflop (or RS). Even using falling
edge flipflop is a very bad idea, some technology
used a not gate before the clock entrance to simulate
the right beaviour.

For large "storage" area like register bank,
memories,caches, TLB, ... we need to create specific
entites that could used specific macrobloc of the
technology (internal memory in Xilinx, compiled SRAM
for semi-custom chip,...)

nicO

 
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