Re: Rep:Re: [f-cpu] register set, latches

[Yann Guidon <whygee@f-cpu.org>]

hi again, again,

nicolas.boulay@ifrance.com wrote:
> -----Message d'origine-----
> De: Yann Guidon <whygee@f-cpu.org>
> A: f-cpu@seul.org
> Date: 12/02/02
> Objet: Re: [f-cpu] register set
> 
> hello,
> <..>
> By the way, if people are "eager" to have a D-ff,
> i could probably reuse the dual-edge flip-flop idea
> and adapt it a bit...
> ----
> >>>> Dual-edge ???? No, we will use normal cell find
> in every technology and not a special thing that
> could only be manualy implemented.

once you have designed the dual-edge cell, you can reuse it instead
of the standard cell. The problem might come from static timing analysis
but the effect is that it will return an operating frequency that is
2x that of the real frequeny.

You seem to like power consumption reduction : dual-edga flip-flops
require almost as many room as a normal one, at least with the sxlib
of Alliance. However, you can drop the clock tree's frequency which
is likely to reduce the power consumption by 25% (granted 50% of
the power is drawn from the clock and its frequency is reduced by 50%).

> Please, think only on rising edge D-flipflop (or RS).
i do that all the time. But dual-edge comes as a replacement
cell which does not change the timing (just halve the clock frequency).

> Even using falling
> edge flipflop is a very bad idea, some technology
> used a not gate before the clock entrance to simulate
> the right beaviour.
"if the tool is broken..."

> For large "storage" area like register bank,
> memories,caches, TLB, ... we need to create specific
> entites that could used specific macrobloc of the
> technology (internal memory in Xilinx, compiled SRAM
> for semi-custom chip,...)

"show me the code" :-)

I looked at LEON specifically for that, and it's poorly explained.

> nicO
WHYGEE
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