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Re: Rep:Re: [f-cpu] register set



hello again,

nicolas.boulay@ifrance.com wrote:> 
> -----Message d'origine-----
> De: Juergen Goeritz <goeritz@oekomm.de>
> A: f-cpu@seul.org
> Date: 12/02/02
> Objet: Re: [f-cpu] register set
> 
> On Tue, 12 Feb 2002, Bruno Bougard wrote:
> > Yann Guidon wrote:
> >
> Usually you can't read and write in the same clock.
> You may be forced to use multiport SRAM.

I didn't answer before to this one, sorry.
No, there are ways (in the FC0 scheduler) to
prevent the same register from being written
at the same time from different ports.


> >>> Double ported SRAM are common. (2 read ports and
> 2 write ports). That's why i don't like the idea to
> have a 3r2w register bank, so we must used "usual"
> vhdl and it will be slow and fat on the silicium.

we have one cycle to perform a read or a write.
"superpipeline" is a way of going at least as fast
as the slowest elementary stage.
But if anyone has VHDL code that instanciates a multiport SRAM,
i'll happily use it. this was the purpose of this thread, btw.

> nicO
> JG
WHYGEE
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