Re: Rep:Re: Re: [f-cpu] No latches, please !

[Michael Riepe <michael@stud.uni-hannover.de>]

On Thu, Feb 14, 2002 at 10:20:16AM -0700, Ben Franchuk wrote:
> nicolas.boulay@ifrance.com wrote:
> > 
> > That's not crazy it's called multiphased logic. You
> > could use 2 or 4 clock phased to synchronise things
> > but i imagine what a nightmarre it could be to debug
> > and to test.
> > 
> But it has two advantages ... 1) A latch is quicker than
> a flip/flop. 2) You need less clock buffering.

A latch is quicker in terms of what? Delay time? Setup time? Clock
frequency?

Latches have one big disadvantage: they can become transparent. In a
pipeline, you don't want that (unless you're willing to work with two
or more different clocks). But they are useful for large memories (e.g.
the caches) where FFs would be too large. The register set may be either
one; personally, I vote for FFs. IMHO there should be no latches at all
in the core (caches excluded) -- otherwise, it would be a complete mess.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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