Re: [f-cpu] testing

[Kim Enkovaara <embo@mpoli.fi>]

> PS: to answer Kim, there must be a dedicated "BIST" unit in the pipeline,
> which overrides the scheduler and performs the integrity check of most
> of the ressources (let's say : 80%). The rest is done with a scan chain
> for the ressources which are not directly addressable by the execution
> pipeline. BIST could be extended later to include a L2 and SDRAM check
> routine (it's not difficult).

Why is is a must to have BIST in the pipeline? It would be much easier to
test it with normal scanchains. For memories MemoryBIST is needed, but
that is quite different story. Also dividing the work between atpg and
bist is quite difficult, how do you calculate real fault coverage? If the
test coverage is not in the ballpark of 95% the chip is not usable for
mass production, you just get too much broken chips to end products.

Also remeber that in ASIC tester you have about 5-10s of time for the
testing. Each second costs real money in the tester, there is no time to
run minutes of tests.

--Kim

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