Re: [f-cpu] testing

[Kim Enkovaara <embo@mpoli.fi>]

> I still feel if you can't design by hand the system may be too complex
> to work properly. If you have system of X alu's and Y thing-a-bobs and Z

I hope I could say so. I have to live with >50M transistor designs :)

> for testing a chip before packaging. Yet even then you your modules with
> proper testing signals as to make gates more visible and break feed back
> loops or long logic paths like carry signals. With FPGA's you don't have
> the gate level testing so for the first round design the sub-modules
> don't need a low level test mode like real silicon would.

The problem is that you have to think about testability during design. At
least the normal rules should be followed: try to minimise clock domains,
clock gating creates problems, don't create reset from internal logic,
do all clock generation at toplevel, avoid latches etc.

> > What if we just use the existing ATPG methodology with scan chains. That
> > is known technology and well tested.
>
> Never heard of it so I can't comment on it. I can understand scan chains
> as serial access of internal sub systems but I think direct tri-stating

ATPG (Automatic Test Pattern Generation) is the way all ASICs currently
are tested. The tools for this are for example Mentor FastScan, Synopsys
TetraMax, Synopsys TestCompiler etc.

--Kim

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