Re: [f-cpu] testing

[Ben Franchuk <bfranchuk@jetnet.ab.ca>]

Kim Enkovaara wrote:

> I hope I could say so. I have to live with >50M transistor designs :)

But since what cpu design I do is a hobby I have 0M transistor designs.
None the less what I have seen of modern cpu designs it still it is hard
work to design something with out all the other factors that come into
play like deadlines and people in suits and it just don't fit in
silicon.

> The problem is that you have to think about testability during design. At
> least the normal rules should be followed: try to minimise clock domains,
> clock gating creates problems, don't create reset from internal logic,
> do all clock generation at toplevel, avoid latches etc.

What is with this fear of latches that everybody has? It is my design if
I want to gate my clocks. :) With what little I have read on CMOS design
see harder to design a single master clock and route to all the
flipflops with clock skew than it is have a multi-phase gated clock and
use latches where clock skew is less critical. But then again my
philosophy is different in design, that  a cpu has to share a memory
bus, and making a CPU fast with the price that it is the only thing that
can the use bus seems counter productive to overall speed of the system.

> ATPG (Automatic Test Pattern Generation) is the way all ASICs currently
> are tested. The tools for this are for example Mentor FastScan, Synopsys
> TetraMax, Synopsys TestCompiler etc.

Well when somebody has several K$ to give me for real proto-type
production of a chip I will refrain from further comments on chip
testing. 

-- 
Ben Franchuk - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html
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