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Re: [f-cpu] about the ongoing work for the "stable" release
Michael Riepe wrote:
> On Fri, Jan 04, 2002 at 02:06:09AM +0100, Yann Guidon wrote:
> > Michael Riepe wrote:
> > > On Wed, Jan 02, 2002 at 04:14:34AM +0100, Yann Guidon wrote:
> > > [...]
> > > > can anybody have a look at "fanout_linear.vhdl" ?
> > > > who can figure why it doesn't work with vanilla ?
> > > It says:
> > > # -- Failure: t: signal has multiple drivers with no resolution function.
> > > This is not true, of course - but vanilla doesn't grok it.
> > obviously ! but if the error message is inacurate, how could i find the error ?
> That's the problem... you can't, normally.
# WHAM ! #
> > > This happens
> > > when certain combinations of range attributes are used (in particular,
> > > 'high and 'low seem to cause problems). If you use explicit ranges,
> > > e.g. `WIDTH-1 downto 0', everything is fine again.
> > This is surprising but this can explains a lot of things.
> > How did you figure that ?
> I had the same problem months ago (fixed it by trial-and-error).
> > > I'll attach a fixed version that works for me. But the recursive version
> > > will have to wait (BTW: did you mean a recursive entity, or a recursive
> > > version of the binary_tree_index function?)
> > At least the linear version is a good start, but a "template" for
> > recursive functions would be a good start. It's not a high priority, though.
> -- BEWARE! UNTESTED CODE!
thank you for the warnin : i have the tendency to trst whatever you do :-D
> function spread (A : in std_ulogic;
> log2_width : in natural)
> return std_ulogic_vector is
> constant L : natural := 2 ** log2_width;
> variably yy : std_ulogic_vector(L-1 downto 0);
> variable tt : std_ulogic;
> if log2_width >= 2 then
> -- L >= 2**2 = 4
> tt := not A;
> yy(L-1 downto L/2) := spread(tt, log2_width - 1);
> yy(L/2-1 downto 0) := spread(tt, log2_width - 1);
> elsif log2_width = 1 then
> -- L = 2**1 = 2
> yy := (others => not A);
> -- L = 2**0 = 1
> yy := (others => A);
> end if;
> return yy;
> end spread;
your use of a function is curious to me, i have the tendency to
prefer generates. however i slowly start to understand why.
> Note: this needs an extra input inverter when log2_width is odd. And I
> don't know what synthesis tools will do with it; they'll probably optimize
> all the inverters away.
my idea is that if the synthesiser is smart enough to optimise the not,
the it must be smart enough to infer the balanced tree again.
Besides this assumption, the "behavioural" and default definition
is pretty clear, it is possible to run the synthesiser with different
options and keep the best ones, so we are not limited by bad tools
and the good tools have some more choices.
> Note #2: I should have made the `fanout factor' a function argument,
> or at least a modifiable constant, instead of just using `2' (I guess
> a 1:3 or 1:4 tree will be much better). With that modification, the
> function might be another candidate for inclusion in `package misc'.
> Provided that it works, of course.
certainly. however 2 is a choice when the circuit is very wide because
the wires are longer. a 4-tree would have more load per node and the
setup time would be longer.
> > - add the INC unit : I found an old "MR" version in the archive and
> > now i have enough VHDL skills to understand it :-)
> Where did you find that (filename)? Must have been a pretty early
> version, I don't even remember that I wrote it. Welcome to the
> `f-cpu stone ages' ;)
Welcome everybody :-)
it's called "inc.vhdl" in the message #5926, the tag is
$Id: inc.vhdl,v 1.2 2000/10/24 00:39:25 michael Exp $
the header is
> Message-ID: <20001024145325.57558@t...>
> Date: Tue, 24 Oct 2000 14:53:25 +0200
> To: firstname.lastname@example.org
> Subject: Re: [f-cpu] (v) F-CPU configuration file
> Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
> "All I wanna do is have a little fun before I die"
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