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[f-cpu] ADD/SUB unit, v2 ?


while reading through the ASU code, i read that
there is no "time" for a 1-bit most-shift
(which would be useful for fractional operations).

I thought about the following solution :
 1) duplicate the unit 
 2) drop the input xors and propagate the change in the
    rest of one of the unit. We thus get one sub and one
    add operation
 3) add the post-shift

Since there is a provision for a simultaneous add/sub
instruction, this is fine :-) The new form of ASU
(optional) would have the same 2 write ports
and the simultaneous add/sub will disallow carry/borrow.

I am thinking about this because i'm currently working on
a 8-bin DCT and most adds are paired with subsractions.
Since i use a derivative of the Winogrgad version,
this is not completely true but the first stages start
like a normal butterfly FFT. The rest is a matter of
scheduling and register allocation...

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