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Re: [f-cpu] "Tree"

> Professional IC designers always work top-down, from spec to gate level,
> through different abstraction level.

That is also my impression. I'm currently part of a huge chip project and
always the works start from specifications at top level by systems people
and ASIC chief designers. After that chief designers try to partition the
design to meaningful and reasonable sized blocks. Then designers can take
that abstraction level and divide their own blocks to smaller blocks. Only
after that should even coding start. If you start from the bottom the top
level picture is very difficult to achieve especially in very complex
chips. CPU is not usually very complex chip compared to some telecom
chips, there top-down design is a necessity.

Of course this top-down approach needs experience about what is possible
and some experiments during planning. Also some blocks need to be defined
at least at pipeline and clock cycle level to see if something is even
possible with given start parameters.

> After P&R, when you have your back annotations, you can run again the
> annotated netlist simulations (for the functionality) and the timing
> analysis with the wire load model extracted from the lay out.

Also in todays advanced flows P&R software can automatically change some
cells in critical paths to faster ones and do all kinds of trickery to
achieve the timing. You don't have that visibility during synthesis. The
netlist after P&R is not usually the same you gave to the vendor.

> synthesizer for IC and it is quite reliable.  I think other more or less
> 'exotic' tools  such Alliance focus more on FPGA and other toy devices.

I think Yann is not talking about Xilinx Alliance. He is talking about a
tool made in french university. It has some resemblance to first versions
of Synopsys in the beginning of 90s. Very small subset of VHDL87 supported
and very limited capabilities.

> Synopsys is quite expensive but some universities get 'educational
> licenses', if there are student amongst you ...

As far as I know the educational licenses are very cheap. It should not be
a big problem for universities. Of course problem is to teach people to
use them. Synopsys DC for example is pain in * to use. Synplify ASIC is
much nicer and very easy to use. But it has to make some track record
first, it seems to be a very good tool.

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