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Re: Tr:Rep:Re: [f-cpu] "Tree"

> I rather have the opinion that after the chip is ready and the
> software starts to use it the problems show up - 2 years lost.
> And imagine - who can spend more than 2 years time to market?

If that happens then there is something wrong in the organization. The
normal way to work succesfully is to have SW people in ASIC design reviews
to give input how they would want the interface. "Half" of my job
currently is to discuss with SW guys about ASIC configuration and pinpoint
their needs also. If they have good suggestions that are easy to do then
they should be part of the ASIC. If the interface fails, I think it
usually pinpoints problems in the communication between USW and HW.

> After 2 years time the premiss may have changed completely.
> Some ASICs were cancelled right when they were finished and
> working.

Cancellation might not mean that HW/SW interface is bad. It might mean
that the whole product is not needed. The world needed other things
than what was an edugated guess from the upper level management. Products
are always gambling, not all of them succeed. I think it is better to
cancel product if there is no need for it.

> Why use more time? If one has HW quirks either the definition
> was sh.. or one has overlooked something fundamental or one
> tried to save time from simulation (pressing schedule).
> And - and that is my biggest concern - one didn't know how
> the software will use the interface later.

If HW side doesnät know how SW wants to use the chip then there is a
problem in communication. Company like that can't survive, you can't fix
that with new description language.  I'm verification guy and at least in
my projects we try to verify the interfaces SW wants to use and in the
same way SW uses the interfaces. But my team uses advanced OO
verification tools to write test benches that are quite comples, more like


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