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Re: [f-cpu] Codesign and SystemC

> SystemC are C++ so your could always start to write
> things in pure software style and then you refine
> your model to have working hardware (after split) (an
> other advantage is the speed 1000 x quicker than VHDL
> simulation !)

But when you add notion of time and concurrent execution to systemC then
the simulation speed dramatically drops. The experiences I have heard is
that the simulation speed is comparable to normal RTl tools. And I think
that is the level where the simulation bottleneck really is. If you change
the abstraction level you have to verify each abstraction level. I have
not seen any formal tools that verify that higher level SystemC
description matches with lower level description. 

If you have tool like that and it works with 5M gate designs then I'm
interested :)


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