Re: [f-cpu] More on Interrupts

[Yann Guidon <whygee@f-cpu.org>]

hi !

Michael Riepe wrote:
> On Fri, Jan 18, 2002 at 08:28:50AM -0700, Ben Franchuk wrote:
> > richard hartny wrote:
> > Nowdays 32 interrupt vectors should be standard.
> 
> For 32-bit CPUs, yes.

from the core's point of view, the IRQ controller
has to send a "IRQ signal" along with a IRQ vector number
(encoded on N bits).

From this point, when the IRQ is acknowleged,
IRQs are disabled (to avoid interruption of the interrupt process)
and the core starts to load the instructions located at
SR_IRQ_BASE + IRQ_VEC*64. When it's loaded, SRB begins
and the handler starts.

If the IRQ wants to become reentering (or allow higher priorities),
it has to configure the SR_IRQ special register where the IRQs are
re-enabled. Before that, it has to prepare itself a frame for storing
its own context, in case SRB occurs again.

The process is reversed when the handler stops : disable IRQ,
free the backup frame (also called 'CMB' for Context Memory Buffer),
trigger reverse SRB.

Is that simple enough ? :-)

This means that the IRQ controller can implement whatever policy it wants :
round-robin, priorities etc. as long as they can still be controlled by
the SR instructions (get and put).

> > Also since most modern OS do a task swap after
> > a interrupt a fast way of of setting task priorities
> > and getting the next sorted task would be useful.
> 
> Since interrupts tend to arrive frequently, interrupt service routines
> should return to the interrupted task as soon as possible. A task
> switch, on the other hand, is rather expensive -- a lot of state has
> to be saved and reloaded, even with SRB.
> 
> Most interrupts deal with I/O - they indicate that data has arrived or
> can be sent, or that some device has changed its state. Usually, none
> of these events triggers an automatic task switch.

However, the basic SRB can be triggered, even if no context is swapped.
SRB was and is still meant to reduce the latencies of ISRs by performing
the register backup almost "hand in hand" with the ISR.

With some smart design (but not tonight because i'm really too tired),
it could be possible to make an exception to the "atomicity" rule
of the SRB mechanism, if the SRB is stopped to restore the instruction
stream that is currently being backed up. This way, "very short" ISRs
(like 16 instructions) could remain short, without even having
to contain context backup/restore instructions.

>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
WHYGEE
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