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[f-cpu] Interrupts, Misquote

I did not say 32 Interrupts should be Standard for 32 Bit Processors.
Again---I have implemented 8 Vectored Priority Interrupts.
For an Encoder, I use the equivalent of an SN74148 Priority Encoder.  Each Interrupt has a dedicated Memory address Pair.  The first is used to store the incremented Program Address, and the second is used to start the context switch.  Since my architecture is M2M; only the A-Register(Accumulator) has to be saved.  I use 3.5 NS SSRAM.
My Language Processor uses 5 of the 8.  They are used for Multiply, Divide, FBC (Fully Buffered Channel) termination Interrupt, IPI (Inter-Processor Interrupt), and one of 128 CRT Monitors from my CICU (Console Interrupt Control Unit).
The IPI is used with a Mailbox in Memory for message passing with my Peripheral Processor. The Mailbox address will be assigned by Software.
The CICU contains a 7 Bit Counter (0 - 127) doing a scan of 128 data lines from a CRT Monitor at a 100 MHz rate.  A Compare stops the scanner, and a controlled serial shift is performed.  When the required number of shifts is performed - the CICU sends an Interrupt Pulse to the Language Processor.  When the Interrupt is permitted, an INA (Input to A-reg) instruction will read data from the CICU and all interrupts are disabled.  The Data contains the Terminal Number and keyboard data/function or mouse address. Completing the CICU read, the counter is released looking for another input. The interrupts will be re-enabled upon completion of the requested task.  Each of the 128 terminals have a dedicated Memory Block.  Etc., Etc.
For the nay-sayers,,,,,,this design has been used on 5 major projects over the years.
Dick Hartney