[f-cpu] (next) crazy idea about immediates

[devik <devik@cdi.cz>]

Hi again,

during night I got other crazy idea - but interesting.
All data needs to be aligned. Ok. We can also suggest
aligning structures to cacheline boundary (and malloc
would return such aligned pointers).
We could support load/store with 5bit immediate value
which would be ORed with physical address in register.
This way there is no need to change LSU working, no
other pipeline stage, no problems with exceptions.
When compiler knows that pointer is aligned to ANY
more than natural boundary it can use indexing because
it indexs INSIDE of single cache-line.

For example when generating epilog I know size of local
store. If I need 10 bytes of it, I align it to 16bytes
and can use indexing to access it.
For latter multiisue 64bit fcpu it allows to schedule
up to LSU 4 64bit insn with single pointer in paralel.

Major problem is when we don't know alignment of pointer -
for example when some program uses it's own allocators
not cache-line aligned. But for example linux kernel
allocator does is correctly.
Gcc should find whether pointer is known to be aligned.

anyone interested ? ;)
devik

*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/