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Re: [f-cpu] Trying to clean up the ROP2 mess
On Thu, Jan 09, 2003 at 01:59:28AM +0100, Yann Guidon wrote:
> hello,
>
> Michael Riepe wrote:
>
> >Subject says it all. We need to make this more regular/orthogonal, and
> >more consistent with the way other instructions work. In particular,
> >we should provide operation variants that
> >
> > - work for 8/16/32/64 bit chunks
> > - mask off the high bits / work on full registers
> > - use direct/and/or mode
> >
> >
>
> did you read one of my mails of yesterday about this subject ?
Yes.
> did you look at FORMAT.txt in the source snapshot ?
Yes.
> why is MUX not included ? (it is performed by the ROP2 unit
> and uses a subset of the functions)
Oh, I forgot that. But there will also be two variants:
mux.size r3, r2, r1 // truncates / zero-extends
smux.size r3, r2, r1 // operates on full word (size ignored)
[...]
> well, we don't converge on these last details but the encoding i
> proposed is able to do that
> (except that there are 2 size fields, one for the writeback size and one
> for the combine chunk size).
That's one of the problems. Since you re-used the SIMD flag for the
additional size flags, there is no longer a way to specify a register-wide
operation (remember that registers may be much wider than 64 bits).
Besides that, the second size flag makes the encoding inconsistent
with the majority of instructions (one goal is to keep the decoder
simple!). For the same reason, I dropped the secondary size flags from
the original `widen' instruction.
> >I will implement this encoding scheme in the next release of my
> >assembler/disassembler/emulator trio.
> >
> you're going to have too much fun : you're insane :-)
Did you try to install my fctools package? ;)
--
Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
"All I wanna do is have a little fun before I die"
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