Rep:Re: [f-cpu] statistics of direct indexing usage

["Nicolas Boulay" <nicolas.boulay@ifrance.com>]

-----Message d'origine-----
De: devik <devik@cdi.cz>
A: <f-cpu@seul.org>
Date: 10/01/03
Objet: Re: [f-cpu] statistics of direct indexing usage

>  From the little i know, the register set, as it is, is the main
problem.
> it's a huge piece of silicon and i count on FC1 (a highly hypothtical
thing)
> to solve this problem (among others). It's probably possible to adapt
> FC0 to reach 1GHz, but it's probably not worth it. It's better to
> target the design of the next architecture towards this barreer,

hmm .. I already though that 6 gates granularity is there
to go very fast. 

>>>From my point of view this was silly. Imagine our multiplier are 6
stage pipeline. In current athlon, the pipeline fpu is  3 stages... But
Cray had used 4 gates granularity and later 8 gates. I can't how much
stage there are but it must be udge.


Probably the register set doesn't follow
the rule ?

>>>That's why ST50/SH5 cpu (which is quite alike f-cpu) use 2-3 stages
for the register access.

PIII which can go 1.2 GHz AFAIK does 32bit add within 1 cycle
latency so they use higher gate-depth per stage than fcpu
which can do obly 8bits. (P4 uses 2 cycles).
Probably they have smaller/simpler register set inside ?

>>>There register is much more complicated with much more access port on
it. But they pipeline the access to it. (TI DSP C64 (16 bits integer)
have 8 read port and 8 write port by register bank, but with 2 or 3
pipestage on a 7 stages pipeline)
nicO

devik

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