Re: [f-cpu] Problem with load/store size flags on >64bit F-CPU

[Yann Guidon <whygee@f-cpu.org>]

hi,

Michael Riepe wrote:

> > Would not be better to have separate SRs for LSU so that
> > they use different size meaning ?
> >    
> <RFC>
>
> The current SR scheme is debatable anyway. Instead of 4 SRs (one for
> each size), we should use a single one, which is faster to save/restore.
> With a single SR_SIZE with four 16-bit chunks, we could address chunk
> sizes up to 65536 bits if the sizes are stored in a linear fashion,
> or 2^65535 if the values are logarithmic. I vote for the latter, btw.
>  
The "status word" that is saved in the CMB contains a compacted
version of the SR_SIZE registers.
We don't expect that an interrupted task can be restarted on another CPU,
so the format can vary (and if that is to happen, then the OS can translate
the format).

I prefer to not think that 64K bit registers will never happen.
things happen at a time or another so the user-visible interface
of the SR_SIZE register has to be kept as simple and limitless as possible.
Saves and restores can then be performed in an adapted way
on later architectures.

In fact, the OS can even trap the writes to the SR_SIZE and update itself
the "compacted version" in the CMB. But i prefer to not speak about
something that i don't know yet how to implement.

YG

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