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Re: [f-cpu] Late answer



hi all !

Ben Franchuk wrote:
> Thomas Lavergne wrote:
> > In the discution about loadcons, personnaly I agree with Michael Riepe
> > solution, because it's possibly a bit more difficult to implement in
> > hardware side (but I'm not sure... ) but it's a lot simpler and more
> > powerfull in software side.
being also a SW guy, i am rather suspicious about the "powerfull" thing.
First, most of the code will be generated by a compiler, so it's a big factor.
Second, i am worried about side effect and how they can be "exploited"
by hand programmers which would learn bad habits.
Finally, remember that the instruction must be easily scheduled on
FC1, FC2, FC3 etc. and nobody has any idea about how they will be
architectured.

> > And personnaly I think that the design of a cpu is to find a good middle
> > between software and hardware.
certainly. This is why an instruction that looks "cool" on one architecture
can become "unwanted" on another. Look at the x86 saga, with the ENTER/LEAVE
or the LEA instructions that are ok, then that are not recommended, etc...
Also remember that F-CPU is based on the RISC principles. Why make the Xbar
more complex when it yields no speedup ?

> > If you look at the x86 architecture, it was designed by hardware man,
> > and look at the 68000 it was designed by software man,
i don't know the full story, but i disagree...
68000 was designed like a "VAX on a chip", 8086 was an extension
to a microcontroller.

> > and all have problems, I think we must keep the two side in mind.
> 
> Right now it is hard to tell just how good the F-Cpu is with software,
> since none has been written. It is in the little werd segments of
> program code that you discover how well or bad your computer design is. Typical
> C code or O/S Calls look good but how well does it behave for a
> handwritten interface for some unknown fast function?
I don't know about the GCC and assembler things, but i am starting
to design a cycle-acurate simulator. It is based on the experience
i got last year with QDCPOC, and the methodology is much more rigid.
the SW hackers will suffer because it uses the HW methodology,
but the results WILL be good. I'll be there to watch if all the
testbenches are correctly written and match the VHDL behaviours.

> Once the documentaion is final, some static programs hand assembled
> and desk debugged for common but dumb routines, block moves, strings
> and multiplies/divides using both simple instructions and higher level
> ones, to get a feel for the machine.
> Playing with my CPU design right now flags are the bottle neck, and need
> to be cleaned up.
flags are a well-known bottleneck, right ?

the risk with MR's shifting loadcons is that it will become
a bottleneck on other architectures.

I meet Etienne Labarre tomorrow at 4PM and i go to Bordeaux on monday.
Stay tuned : this summer will be VERY HOT...

WHYGEE
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