[f-cpu] Free synthesis tool for Verilog and other links

[Michael Opdenacker <zumbi2@netcourrier.com>]

Hello,

As I told some of you last week in the LSM event, a free synthesis tool
exists for Verilog (unfortunately not for VHDL):

http://icarus.com/eda/verilog/

Here is also a nice page full of useful links, for those who may not
know it:

http://www.eedesign.com/resources/opensourcelinks.html

Good luck for your great project!

	@:-)

	Cheers,

	Michael.

-- 

Michael Opdenacker
http://michaelo.free.fr/

MATH AND ALCOHOL DON'T MIX!

       Please, don't drink and derive.

       Mathematicians
       Against
       Drunk
       Deriving

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