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Re: [f-cpu] Conditionnal Load and Store



On Fri, Jul 26, 2002 at 04:57:32PM +0200, Yann Guidon wrote:
[...]
> conditional loads/stores are a corollary of the conditional moves.
> 
> IIRC it appeared that these instructions were in fact needed,
> when we were discussing about the semaphores done with LL/SC.
> "Store conditional" is this thing.

That's a very different kind of instruction (atomic read-write).

> By the way : condition 3 is still reserved for FP, but we could
> simply connect it to the LSU : LL/SC would then not need any specific
> opcode. it sounds easy and logical, what do others think ?

Definitely no. move/jump has NOTHING to do with ll/sc, and they should
have different opcodes.

[...]
> ***************************************************************
> HOWEVER I HAVE A BIG PROBLEM WITH THE MSB CONDITION CODE !
> i believe i told this on the list, but no solution is known yet.
> 
> Currently, the "MSB" condition just takes the 63th bit of the
> pointed register. But what about larger registers ? what about
> small integers ?

Proposed fixes:

	a) always use bit 63
	b) always use the most significant bit
	c) drop the MSB condition thing altogether
	d) never build an F-CPU with registers wider than 64 bits

I like c) because it makes things simpler. We can drop the unused
condition, too (testing for NaNs is too complex anyway). If somebody
really wants to test for any other bit than the LSB, he shall either
shift/rotate it in place or mask the other bits off (bitopt/btst
instruction) and use a zero/notzero condition.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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