Re: [f-cpu] Conditionnal Load and Store

[nico <nicolas.boulay@ifrance.com>]

Michael Riepe a écrit :
> 
> On Fri, Jul 26, 2002 at 04:57:32PM +0200, Yann Guidon wrote:
> [...]
> > conditional loads/stores are a corollary of the conditional moves.
> >
> > IIRC it appeared that these instructions were in fact needed,
> > when we were discussing about the semaphores done with LL/SC.
> > "Store conditional" is this thing.
> 
> That's a very different kind of instruction (atomic read-write).
> 
> > By the way : condition 3 is still reserved for FP, but we could
> > simply connect it to the LSU : LL/SC would then not need any specific
> > opcode. it sounds easy and logical, what do others think ?
> 
> Definitely no. move/jump has NOTHING to do with ll/sc, and they should
> have different opcodes.
> 
> [...]
> > ***************************************************************
> > HOWEVER I HAVE A BIG PROBLEM WITH THE MSB CONDITION CODE !
> > i believe i told this on the list, but no solution is known yet.
> >
> > Currently, the "MSB" condition just takes the 63th bit of the
> > pointed register. But what about larger registers ? what about
> > small integers ?
> 
> Proposed fixes:
> 
>         a) always use bit 63
>         b) always use the most significant bit
>         c) drop the MSB condition thing altogether
>         d) never build an F-CPU with registers wider than 64 bits
> 

Can we used the usual SIMD bits ? so we will use the 63 or the 31 or the
15 or the 7 bits.

d) solution aren't possible ! ;p (i'm for thinking with 256 bits
registers). I think in that case that we used the register as a scalar
value (not a packed one for SIMD stuff). In the case of 256 bits
registers, the scalar chunk of 64-32-16-8 bits are still there. If "int"
is 64 bits long it's not a hard point to always read the 63th bits of
the register. Maybe the 31th will be better (it's a true "C int" size).

solution b) have no sense on a 256 bits register set. It will read the
255th bit but we work only with the 0-63 first bit on scalar operation
(that's an other point but : "What a waste by only using a quarter of
the register !" (why not using 2 registers set : on scalar and the other
SIMD)).


nicO

> I like c) because it makes things simpler. We can drop the unused
> condition, too (testing for NaNs is too complex anyway). If somebody
> really wants to test for any other bit than the LSB, he shall either
> shift/rotate it in place or mask the other bits off (bitopt/btst
> instruction) and use a zero/notzero condition.
> 
> --
>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
>  "All I wanna do is have a little fun before I die"
> *************************************************************
> To unsubscribe, send an e-mail to majordomo@seul.org with
> unsubscribe f-cpu       in the body. http://f-cpu.seul.org/
*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/